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TINA supports 4
Hardware Description Languages (HDL):
VHDL, Verilog, Verilog-A and Verilog-AMS
Digital VHDL
Simulation
VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware
Description Language) is an IEEE- standard hardware description
language used by electronic designers to describe and simulate
their chips and systems prior to fabrication.
TINA includes a
powerful digital VHDL simulation engine. Any digital circuit in
TINA can be automatically converted a VHDL code and analyzed as
a VHDL design. In addition, you can analyze the wide range of
hardware available in VHDL and define your own digital
components and hardware in VHDL. The great advantage of VHDL is
not only that it is a IEEE standard, but also that can be
realized automatically in programmable logic devices such as
FPGAs and CPLDs.
TINA can generate
a synthesizable VHDL code along with the corresponding UCF file
if the Generate synthesizable code checkbox is set in the
Analysis/Options menu. You can save the created VHD and UCF
files with the “Create VHD & UCF File” command in the T&M menu.
You can read these files with Xilinx’s free utility Webpack,
generate the bit-stream file describing the implementation of
the design and then upload it to Xilinx FPGA chips.
Digital Verilog
Simulation
TINA also includes a powerful digital Verilog simulation engine.
The advantage of Verilog compared to VHDL that it is easier to
learn and understand, however there are more features in VHDL.
TINA can translate
the Verilog models and the other digital components to
synthesizable VHDL code and, using the Xilinx’s Webpack
software, you can generate the bit stream file describing the
implementation of the design and then upload it to Xilinx FPGA
chips.
Digital Verilog-A
Simulation
Today the most widely used
language to describe electronics circuits and device models is
the Spice netlist format (1973). However the Spice netlists are
often hard to read and understand, and they lack a lot of the
functionalities of programming languages which engineers would
need while creating models and simulation.
The relatively new
Verilog-A language (1995) provides an alternative method with an
easy to read programming language style C like syntax. Thus
Verilog-A is a suitable successor of the SPICE netlists for
describing circuit topologies.
Digital Verilog-AMS Simulation
An even more
sophisticated method of describing electronics circuit,
containing both analog and digital components is the Verilog-AMS
language. As we observed earlier, Verilog-AMS is a derivative of
of the purely digital Verilog extended with the purely analog
Verilog A and an interface for the connection of the analog and
digital parts.
Most of the device
libraries of TINA are in Spice netlist format. However you can
already create and import models and place TINA macros in
Verilog-A and Verilog-AMS format. You can find several language
examples, device models, and circuits in the Examples\Verilog A
folder of TINA
DesignWare, Inc., 35 Pleasant St., Suite 3C, Meriden, CT 06450-7596
Tel: (1) 203 630 7069
Fax: (1) 203 630 2818 Email:
info@designwareinc.com
Latest revision: 01/02/2017. |
TINATM